Architectures and circuits for ultra-low-power integrated wake-up radios

A Wake-Up Radio (WuRX) is an enabling technology for the Internet-of-Things. It i is composed of two subsystems: the Analog Front-End (AFE) and the Baseband Logic (BBL). AFE task is to turn the input OOK-modulated signal into a stream of bits. WuRX AFEs can be classified in clocked or clockless. Clocked AFEs leverage the use of an always-on clock, which inevitably implies a dramatic increase in power consumption, while clocked AFEs do not. Therefore, this thesis focuses on ultra-low-power WuRXs featuring clockless AFEs. The Baseband Logic (BBL) compares the received bitstream with the address of the specific node and, if the two match, issues a Wake-Up interrupt. In particular, the packet containing the address of the node is called Wake-Up Packet (WUP). WuRX performances are conventionally evaluated on two metrics: Missed Detection Rate (MDR) and False Alarm Rate (FAR). The first quantifies its detection capability while the second the frequency of false wake-ups due to noise or interferers. While AFE can detect infinite bits, baseband logic architectures, due to the phase/frequency mismatch between received data and clock, can process WUPs of limited length (8 up to 63 bits). Such lengths turn out to be not acceptable in case the WuRX must tolerate very low FARs or receive more sophisticated and encrypted WUPs. In particular, the latter is a key feature to enhance the security of WSANs in private or sensitive data-processing applications. To overcome the issues related to the maximum WUP length, this thesis proposes a nanowatt Gated Oscillator Clock and Data Recovery (GO-CDR) circuit which enables the WuRX to receive hundreds of bits. Another key-feature proposed in this thesis involves the generation of the threshold voltage for the continuous time comparator within the clockless AFE.