Characterization and Modeling of Semiconductor Power Devices Reliability

This thesis aims at studying, characterizing and modeling the trapping and de-trapping mechanisms occurring during the ON-state operation mode and leading to the degradation of semiconductor power devices. In this operating condition, the combined effect of moderate electric fields, high currents and temperatures due to self-heating effects can seriously affect the long-term reliability leading to device failure. Detailed analyses are performed on both silicon and gallium nitride based technologies by means of accelerated life test methods and electro-thermal simulations, aimed at understanding the physical origins of the degradation. In particular, this thesis provides the following contributions: i) the role of the interface and oxide trapped charge induced by negative bias temperature instability (NBTI) stress in p-channel Si-based U-MOSFETs is investigated. The impact of relevant electrical and physical parameters, such as stress voltage, recovery voltage and temperature, is accounted for and proper models are also proposed. In the field of innovative semiconductor power devices, this work focuses on the study of GaN-based devices. In particular, three different subtopics are considered: ii) a thermal model, accounting for the temperature dependence of the thermal boundary resistance (TBR), is implemented in TCAD simulator in order to realistically model self-heating effects in GaN-based power devices; iii) the degradation mechanisms induced by ON-state stress in GaN-based Schottky barrier diodes (SBDs) are proposed by analyzing their dependence on the device geometry; iv) the trapping mechanisms underlying the time-dependent gate breakdown and their effects on the performance of GaN-based power HEMTs with p-type gate are investigated, and an original empirical model representing the relationship between gate leakage current and time to failure is proposed.