Models development of new cells protection for electrostatic discharges integrated in smart power technology

In this thesis, a TCAD approach for the investigation of the safe operating area and the power to failure performances of trading ESD protection is presented. The proposed approach is used to investigate power to failure condition for very short stress times, under 1ns, comparing the theoretical expected trends to the predicted and measured ones of the device under test. The physical reasoning of the lack in performance experiences in the proposed devices is presented together with a possible solution. The same proposed approach is applied also to other devices to study their holding voltage condition in correlation with the failure. In the first part of this thesis, a detailed review of the ESD models and characterization techniques is presented together with the physical models that are peculiar of and ESD event. In addition, ESD physics and operational mode of basic components is explained. In the second part, the operating conditions of a new ESD clamp based on BJT transistors is presented. The main physical mechanisms that drive the bipolar transistors into failure conditions during a very fast stress are analyzed and further investigated through geometrical modifications. In the third part, a conventional SCR-LDMOS ESD clamp is investigated as case study to learn the role played by the physical mechanisms and the two bipolar transistors when the device is in holding-voltage conditions. Several layout and geometrical modifications have been performed on the standard device to study and show the effect over the IV curve and the resulting failure conditions.