Design of low-power analog circuits for wake-up radio in IoT nodes

The goal of this Ph.D. research activity is the design of an Analog Front End which receives OOK-modulated input signals with RF carrier frequencies in the Sub-GHz ISM band and has a power consumption in the order of nanoWatts, thus targeting medium range IoT applications, i.e. with a wake-up distance within 100 meters. Over the course of this Ph.D. activity, three prototypes have been designed using a 90-nm STMicroelectronics technology. The main challenge this topic poses is the sensitivity-power trade-off, that is a longer wake-up distance requires a higher power consumption. All proposed implementations are clockless and leverage the second-order non-linearities of a MOSFET in subthreshold for envelope extraction. The first and second prototypes include an active Envelope Detector, a band-pass and a low-pass one, respectively, whereas the third prototype implements a passive Envelope Detector. The first two prototypes have been tested while the third one is currently under fabrication. Measurements on the first prototype have yielded a -46-dBm sensitivity at 771 MHz with a 36-nW power consumption over a 1.2-V supply and a 2-kbit/s bitrate, resulting in 106.9-dB Figure of Merit. Measurements on the second one have yielded a projected -52.3-dBm sensitivity at 433 MHz with a 12.9-nW power consumption over a 0.6-V supply and a 1-kbit/s bitrate, resulting in 116.2-dB Figure of Merit. Simulations of the third one have yielded a -63.1-dBm estimated sensitivity at 433 MHz with a 16.8-nW power consumption over a 0.6-V supply and a 0.5-kbit/s bitrate, resulting in 124.3-dB Figure of Merit.