Analog in-memory computing based on phase-change memory: programming algorithms and applications.

In the era of Artificial Intelligence (AI), many applications demand low-power computation over large datasets. Conventional digital computers face performance limitations due to the inherent communication bottleneck of the Von Neumann architecture, which requires frequent data transfers between memory and processing units. To address this challenge, novel computational paradigms have emerged. Among these, Analog In-Memory Computing (AIMC), based on resistive memory devices, offers a promising non-Von Neumann approach for fast and energy-efficient execution of matrix-vector multiplications (MVMs). Since MVMs constitute a significant portion of the workload in deep learning inference, AIMC’s ability to perform these operations with constant time complexity (O(1)) can substantially enhance both speed and energy efficiency. AIMC performs analog computation directly within resistive memory by leveraging the physical properties of memory devices and fundamental electrical principles such as Ohm’s and Kirchhoff’s laws. Among the candidate technologies, Phase-Change Memory (PCM) is particularly attractive due to its multi-bit storage capability, long retention, and compatibility with standard CMOS fabrication processes. However, PCM devices exhibit unique non-idealities, including non-linear current-voltage characteristics, stochastic conductance drift over time, and variability in programmed states. These factors degrade the accuracy of PCM-based analog accelerators and consequently impact overall application-level performance. This thesis addresses challenges at the programming level by proposing novel multilevel algorithm for PCM devices, validating them through a wide range of applications and hardware characterization. In particular, two major types of programming algorithms are addressed: a single-cell programming algorithm and a dual-cell programming algorithm. Both aim to minimize the drift effect and improve accuracy using various strategies, achieving significant performance improvements across different applications, such as binary pattern matching recognition, motor control stability preservation, and MNIST classification through Deep Neural Network (DNN) inference. These aspects were studied by leveraging two AIMC prototypes designed to mitigate some PCM non-idealities from a hardware perspective.