Power-thermal modeling and management of modern chiplet-based processors

As semiconductor scaling approaches the limits of monolithic integration, chiplet-based architectures have become a key enabler of continued performance and energy-efficiency improvements in high-performance computing (HPC) processors. By partitioning large dies into smaller chiplets interconnected through high-bandwidth die-to-die links, designers improve yield and enable heterogeneous integration. However, this architectural shift introduces new power and thermal management challenges, including cross-chiplet thermal coupling, localized hotspots, and performance degradation due to thermal throttling. Efficient operation therefore requires coordinated and low-latency control across multiple on-die Power-Management Subsystems (PCSs). This dissertation addresses these challenges through four complementary contributions spanning control architectures, communication infrastructures, and data-driven modeling. First, it presents ControlPULP, an open and scalable RISC-V–based PCS architecture for fine-grained power and thermal management. Within this development, the author’s contribution focuses on the design and integration of a standardized communication interface between the Operating System Power Management (OSPM) layer and the PCS, based on the SCMI specification, enabling delegation-based runtime power management in many-core systems. Second, it provides a fine-grained experimental characterization of standardized power-management interfaces in modern HPC processors. Using an FPGA-based hardware-in-the-loop platform and the Linux SCMI stack, the study quantifies end-to-end communication delays and shows that firmware optimizations can reduce control latency from 1.3 ms to 114 μs, improving execution time by up to 3%. Third, it proposes a user-space communication substrate for distributed PCS networks based on Micro XRCE-DDS, introducing a shared-memory transport that removes kernel bottlenecks and enables scalable, low-latency coordination with predictable memory overhead. Finally, it develops a compact empirical thermal–power modeling methodology for many-core chiplet processors, combining performance-counter-based power estimation with distributed MISO-ARX thermal identification and enabling floorplan extraction directly from silicon measurements. Together, these contributions advance open, distributed, and predictive power–thermal management for next-generation chiplet-based HPC systems.