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Abstract
Modern embedded devices must sense, interpret, and act on the edge within tight power and size budgets. Closing the loop locally demands low latency, predictable timing, and robust operation from sensors through control. In these nodes, moving and converting data is the dominant cost, so placing compute near the source and minimizing data exchange delivers the largest gains. Because power, interfaces, and form-factor requirements differ among device classes, a single uniform architecture cannot meet all needs. In contrast, effective edge platforms co-design compute, memory, and I/O as heterogeneous System-on-Chips (SoCs) that pair general-purpose processors with task-tuned accelerators, combining flexibility with superior energy–performance through hardware–software co-design and system-level validation. This thesis addresses this challenge and proposes four silicon-proven SoCs for embedded devices in an intentional progression of on-chip heterogeneity. First, Buckbeak pairs a general-purpose core with a reconfigurable cluster of two vector engines, adapting their form-factor execution at runtime to enable efficient mixed scalar–vector workloads near the sensor. Next, Echoes augments a general-purpose core with a frequency-domain Fast Fourier Transform accelerator to process multi-channel digital audio interface and convert streams to spectra with low overhead. Then, Maestro combines a general-purpose core with both frequency-domain and vector–tensor engines to support end-to-end signal processing and learning in wearable ultrasound. Finally, AlSaqr integrates eight parallel general-purpose processing cores coupled with a low-precision tensor accelerator and cryptographic units under a hardware Root of Trust along with a dual-core Linux-capable host, enabling secure and autonomous navigation for nano-drones. Coupled through shared memories to minimize data movement, these complementary approaches demonstrate how tailoring heterogeneity to domain needs can sustain on-device processing for applications ranging from audio and ultrasound wearables to drones and robotics systems, all within ultra-low-power envelopes compatible with small batteries and compact form factors.
Abstract
Modern embedded devices must sense, interpret, and act on the edge within tight power and size budgets. Closing the loop locally demands low latency, predictable timing, and robust operation from sensors through control. In these nodes, moving and converting data is the dominant cost, so placing compute near the source and minimizing data exchange delivers the largest gains. Because power, interfaces, and form-factor requirements differ among device classes, a single uniform architecture cannot meet all needs. In contrast, effective edge platforms co-design compute, memory, and I/O as heterogeneous System-on-Chips (SoCs) that pair general-purpose processors with task-tuned accelerators, combining flexibility with superior energy–performance through hardware–software co-design and system-level validation. This thesis addresses this challenge and proposes four silicon-proven SoCs for embedded devices in an intentional progression of on-chip heterogeneity. First, Buckbeak pairs a general-purpose core with a reconfigurable cluster of two vector engines, adapting their form-factor execution at runtime to enable efficient mixed scalar–vector workloads near the sensor. Next, Echoes augments a general-purpose core with a frequency-domain Fast Fourier Transform accelerator to process multi-channel digital audio interface and convert streams to spectra with low overhead. Then, Maestro combines a general-purpose core with both frequency-domain and vector–tensor engines to support end-to-end signal processing and learning in wearable ultrasound. Finally, AlSaqr integrates eight parallel general-purpose processing cores coupled with a low-precision tensor accelerator and cryptographic units under a hardware Root of Trust along with a dual-core Linux-capable host, enabling secure and autonomous navigation for nano-drones. Coupled through shared memories to minimize data movement, these complementary approaches demonstrate how tailoring heterogeneity to domain needs can sustain on-device processing for applications ranging from audio and ultrasound wearables to drones and robotics systems, all within ultra-low-power envelopes compatible with small batteries and compact form factors.
Tipologia del documento
Tesi di dottorato
Autore
Sinigaglia, Mattia
Supervisore
Co-supervisore
Dottorato di ricerca
Ciclo
38
Coordinatore
Settore disciplinare
Settore concorsuale
Parole chiave
System-on-Chip, embedded computing, digital architecture
Data di discussione
27 Marzo 2026
URI
Altri metadati
Tipologia del documento
Tesi di dottorato
Autore
Sinigaglia, Mattia
Supervisore
Co-supervisore
Dottorato di ricerca
Ciclo
38
Coordinatore
Settore disciplinare
Settore concorsuale
Parole chiave
System-on-Chip, embedded computing, digital architecture
Data di discussione
27 Marzo 2026
URI
Gestione del documento: